Description of the Prior Art
In many communications applications, a conversion is performed between data in serial format and parallel format. For example, a Universal Asynchronous Receiver/Transmitter (UART) is used to send and receive serial data to and from terminal equipment that operates on data words, with each word typically comprising 8 data bits. The terminal equipment may comprise a modem connected to a personal computer (PC), for example. In one widely used UART, the National 16550, there is a 16 word first-in, first-out memory (FIFO) for each of the transmit and receive data paths. In addition to the 8 data bits, each receive word has 3 associated error bits. These error bits allow the receiving modem to determine whether errors in transmission have occurred, and to give an indication of the nature of the errors. In this manner, retransmission of data front the transmit modem may be requested to correct for missing or corrupted data.
An illustration of the receive FIFO is given in FIG. 1, wherein the receive FIFO 100 holds 8 bits of data in each receive word (e.g., 101), and 3 bits of error information (e.g., 102) associated with each receive word. A status flag (not shown) in the 16550 is used to indicate whether any word in the FIFO has an error bit set. This bit can be used by PC driver software to simplify and speed up the reading of data. By reading this bit (once) the driver software knows if the data in the FIFO is error free or not. If it is error tree, then the PC can quickly read the block of data, and ignore (i.e. NOT READ, thus saving time) the error information. If an error does exist, it can slowly flush the FIFO (by reading twice, once to get the data word, and a second read to get error status) and determine what the error is, and what its consequences are, or simply ask the far side to retransmit the block of data. When the data in the FIFO is over-written with error-free data, the error flag is reset.
Referring to FIG. 2, the status bit is computed by "OR"ing the error bits (E.sub.1, E.sub.2, E.sub.3) in each word of the FIFO. Since there are 16 words with 3 errors bits per word, this requires a 16.times.3=48 bit OR operation. This may be accomplished with a single OR gate having 48 inputs, or more typically with multiple OR gates (e.g., 201,202,203) having a fewer number of inputs, as illustrated. With the increase in modem speed, there is interest in increasing the number of words in the FIFOs to 32 or even 64 words, which increases the width of the "OR" gate to 96 or 192 inputs. This results in larger and larger arrays of OR-ing, in addition to the circuitry required to access the error bits of the FIFO. As FIFO sizes increase, this means larger circuits and delays in computing the status bit. In addition, a means must be provided in the prior-art technique for clearing the error bits when read. Otherwise, the OR circuitry will falsely show an error, even after the word has been read.